|
extern module and("and.sch"); # a kicad schematic in the same directory which defines some input/output signals and wires them together in some way
|
|
extern module or("or.sch"); # same thing, but for or
|
|
extern module xor("xor.sch");
|
|
|
|
# a binary half adder
|
|
module half_adder(input a, input b, output sum, output carryOut)
|
|
{
|
|
xor(a, b, sum);
|
|
and(a, b, carryOut);
|
|
}
|
|
|
|
# a binary full adder
|
|
module full_adder(input a, input b, input carryIn, output sum, output carryOut)
|
|
{
|
|
signal sum1;
|
|
signal carry1;
|
|
signal carry2;
|
|
|
|
half_adder(a, b, sum1, carry1);
|
|
half_adder(sum1, carryIn, sum, carry2);
|
|
or(carry1, carry2, carryOut);
|
|
}
|
|
|
|
# a byte full adder
|
|
# takes in busses(arrays of signals)
|
|
module byte_adder(input A[0:7], input B[0:7], input carryIn, output Sum[0:7], output carryOut)
|
|
{
|
|
signal Carries[0:6];
|
|
full_adder(A[0], B[0], carryIn, Sum[0], carry[0]);
|
|
full_adder(A[1], B[1], carry[0], Sum[1], carry[1]);
|
|
full_adder(A[2], B[2], carry[1], Sum[2], carry[2]);
|
|
full_adder(A[3], B[3], carry[2], Sum[3], carry[3]);
|
|
full_adder(A[4], B[4], carry[3], Sum[4], carry[4]);
|
|
full_adder(A[5], B[5], carry[4], Sum[5], carry[5]);
|
|
full_adder(A[6], B[6], carry[5], Sum[6], carry[6]);
|
|
full_adder(A[7], B[7], carry[6], Sum[7], carryOut);
|
|
}
|
|
|
|
# this is what gets converted into a schematic
|
|
# it's just a re-export of the byte adder.
|
|
module main(input A[0:7], input B[0:7], input cIn, output Sum[0:7], output cOut)
|
|
{
|
|
byte_adder(A, B, cIn, Sum, cOut);
|
|
}
|
|
|
|
# tests
|
|
|
|
# we need to define how and, or, xor work
|
|
# compiler will look at the signals to figure out what are inputs and what are outputs
|
|
expect and(0, 0, 0);
|
|
expect and(0, 1, 0);
|
|
expect and(1, 0, 0);
|
|
expect and(1, 1, 1); # can also write `expect and(HIGH, HIGH, HIGH)` - HIGH = 1 and LOW = 0; The compiler doesn't care
|
|
|
|
test "adder works" # start with "test", then the name of the test case
|
|
{
|
|
signal Sum[0:7];
|
|
signal cOut;
|
|
# numbers are automatically converted into bus values
|
|
byte_adder(2, 3, LOW, Sum, cOut);
|
|
assert_equal(5, Sum);
|
|
assert_equal(LOW, cOut);
|
|
}
|